Yu-Guang Chen

Orcid: 0000-0002-9616-7379

According to our database1, Yu-Guang Chen authored at least 34 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
DRC Violation Prediction After Global Route Through Convolutional Neural Network.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Invited Paper: Overview of 2023 CAD Contest at ICCAD.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs.
Proceedings of the Asia Pacific Signal and Information Processing Association Annual Summit and Conference, 2023

2022
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine.
Proceedings of the 19th International SoC Design Conference, 2022

Overview of 2022 CAD Contest at ICCAD.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
An efficient <i>NBTI</i>-aware wake-up strategy: Concept, design, and manipulation.
Integr., 2021

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions.
Proceedings of the 18th International SoC Design Conference, 2021

Overview of 2021 CAD Contest at ICCAD.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

ROAD: Improving Reliability of Multi-core System via Asymmetric Aging.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
An efficient NBTI-aware wake-up strategy for power-gated designs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2012
Efficient on-line module-level wake-up scheduling for high performance multi-module designs.
Proceedings of the International Symposium on Physical Design, 2012

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
NBTI-aware power gating design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A novel fuzzy direct torque control system for three-level inverter-fed induction machine.
Int. J. Autom. Comput., 2010

2006
Tracers placement for IP traceback against DDoS attacks.
Proceedings of the International Conference on Wireless Communications and Mobile Computing, 2006


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