Yu-Guang Chen

According to our database1, Yu-Guang Chen authored at least 18 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

ROAD: Improving Reliability of Multi-core System via Asymmetric Aging.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
An efficient NBTI-aware wake-up strategy for power-gated designs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2012
Efficient on-line module-level wake-up scheduling for high performance multi-module designs.
Proceedings of the International Symposium on Physical Design, 2012

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
NBTI-aware power gating design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A novel fuzzy direct torque control system for three-level inverter-fed induction machine.
Int. J. Autom. Comput., 2010

2006
Tracers placement for IP traceback against DDoS attacks.
Proceedings of the International Conference on Wireless Communications and Mobile Computing, 2006


  Loading...