Kai-Chiang Wu

According to our database1, Kai-Chiang Wu authored at least 32 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Making Aging Useful by Recycling Aging-induced Clock Skew.
ACM Trans. Design Autom. Electr. Syst., 2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Test Methodology for Defect-based Bridge Faults.
Proceedings of the IEEE International Test Conference in Asia, 2020

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
Layout-Based Dual-Cell-Aware Tests.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Methodology of Generating Timing-Slack-Based Cell-Aware Tests.
Proceedings of the IEEE International Test Conference, 2019

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Aging-aware chip health prediction adopting an innovative monitoring strategy.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Sensor-Based Time Speculation in the Presence of Timing Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MAUI: Making aging useful, intentionally.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Lifetime Reliability Trojan Based on Exploring Malicious Aging.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Fast WAT test structure for measuring Vt variance based on latch-based comparators.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Workload-aware lifetime Trojan based on statistical aging manipulation.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

Analysis and optimization of variable-latency designs in the presence of timing variability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment.
IEEE Trans. Very Large Scale Integr. Syst., 2014

NBTI and Leakage Reduction Using ILP-Based Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2014

BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Aging-aware timing analysis and optimization considering path sensitization.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Clock skew scheduling for soft-error-tolerant sequential circuits.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Joint logic restructuring and pin reordering against NBTI-induced performance degradation.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Power-aware soft error hardening via selective voltage scaling.
Proceedings of the 26th International Conference on Computer Design, 2008

Process variability-aware transient fault modeling and analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Soft error rate reduction using redundancy addition and removal.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors.
IEEE Trans. Control. Syst. Technol., 2007

2006
Delay variation tolerance for domino circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004
Re-synthesis for delay variation tolerance.
Proceedings of the 41th Design Automation Conference, 2004


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