Nitanshu Chauhan

Orcid: 0000-0002-7993-3449

According to our database1, Nitanshu Chauhan authored at least 10 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology.
Microelectron. J., 2021

Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Traps Based Reliability Barrier on Performance and Revealing Early Ageing in Negative Capacitance FET.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Variability Effects in FinFET Transistors and Emerging NC-FinFET.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019
Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019


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