Norhayati Soin

Orcid: 0000-0002-8775-1346

According to our database1, Norhayati Soin authored at least 14 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
On Wafer Noise Figure De-Embedding Method for CMOS Differential LNA.
IEICE Trans. Electron., 2020

Development and Characterization of Freestanding Poly (Methyl Methacrylate)/Monolayer Graphene Membrane.
IEEE Access, 2020

2019
Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator.
IET Comput. Digit. Tech., 2019

Comprehensive Study on RF-MEMS Switches Used for 5G Scenario.
IEEE Access, 2019

2016
Design of graphene-based MEMS intracranial pressure sensor.
Proceedings of the 2016 IEEE International Symposium on Medical Measurements and Applications, 2016

2014
Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Defects evolution involving interface dispersion approaches in high-k/metal-gate deep-submicron CMOS.
Microelectron. Reliab., 2014

Energy distribution of positive charges in high-k dielectric.
Microelectron. Reliab., 2014

2013
Theoretical development and critical analysis of burst frequency equations for passive valves on centrifugal microfluidic platforms.
Medical Biol. Eng. Comput., 2013

Multi-level 3D implementation of thermo-pneumatic pumping on centrifugal microfluidic CD platforms.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
Reduction of annealed-induced wafer defects in dual-damascene copper interconnects.
Microelectron. Reliab., 2012

Trench DMOS interface trap characterization by three-terminal charge pumping measurement.
Microelectron. Reliab., 2012

2010
NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations.
Microelectron. Reliab., 2010

Low power clock gates optimization for clock tree distribution.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010


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