Guido Groeseneken
Orcid: 0000-0003-3763-2098Affiliations:
- Catholic University of Leuven, Belgium
According to our database1,
Guido Groeseneken
authored at least 90 papers
between 1998 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2005, "For his contributions to the physical understanding and the modeling of reliability of metal oxide semiconductor field effect transistors.".
Timeline
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Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Physics-based device aging modelling framework for accurate circuit reliability assessment.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
The properties, effect and extraction of localized defect profiles from degraded FET characteristics.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.
Proceedings of the IEEE International Memory Workshop, 2021
2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Full (V<sub>g</sub>, V<sub>d</sub>) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
Experimental calibration of the temperature dependence of the heterojunction bandgap in III-V tunneling devices.
Proceedings of the Device Research Conference, 2019
Proceedings of the Device Research Conference, 2019
2018
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 76th Device Research Conference, 2018
2017
IEEE Des. Test, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
From planar to vertical capacitors: A step towards ferroelectric V-FeFET integration.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015
Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Engineering of a TiN\Al2O3\(Hf, Al)O2\Ta2O5\Hf RRAM cell for fast operation at low current.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Stability evaluation of Au-free Ohmic contacts on AlGaN/GaN HEMTs under a constant current stress.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Determination of energy and spatial distribution of oxide border traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As MOS capacitors from capacitance-voltage characteristics measured at various temperatures.
Microelectron. Reliab., 2014
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Microelectron. Reliab., 2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Impact of design factors and environment on the ESD sensitivity of MEMS micromirrors.
Microelectron. Reliab., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2009
IEEE Trans. Instrum. Meas., 2009
Microelectron. Reliab., 2009
Microelectron. Reliab., 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Microelectron. Reliab., 2007
Microelectron. Reliab., 2007
Microelectron. Reliab., 2007
Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability.
Microelectron. Reliab., 2007
Negative bias temperature instabilities in HfSiO(N)-based MOSFETs: Electrical characterization and modeling.
Microelectron. Reliab., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs - Concepts, constraints and solutions.
Microelectron. Reliab., 2006
Microelectron. Reliab., 2006
2005
ESD circuit model based protection network optimisation for extended-voltage NMOS drivers.
Microelectron. Reliab., 2005
Microelectron. Reliab., 2005
Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability.
Microelectron. Reliab., 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits.
Microelectron. Reliab., 2004
Microelectron. Reliab., 2004
2003
High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.
Microelectron. Reliab., 2003
2002
Microelectron. Reliab., 2002
Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study.
Microelectron. Reliab., 2002
2001
A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation.
Microelectron. Reliab., 2001
Microelectron. Reliab., 2001
1999
1998
IEEE J. Solid State Circuits, 1998