J. M. Pierre Langlois
Orcid: 0000-0003-1721-2520Affiliations:
- Polytechnique Montréal
According to our database1,
J. M. Pierre Langlois
authored at least 94 papers
between 2002 and 2023.
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Bibliography
2023
ACM Trans. Archit. Code Optim., March, 2023
CoRR, 2023
Iterative pruning algorithm for efficient look-up table implementation of binary neural networks.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
2020
J. Signal Process. Syst., 2020
Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of Machine Learning and Systems 2020, 2020
Proceedings of the 21st IEEE International Conference on High Performance Switching and Routing, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
2019
SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics.
IEEE/ACM Trans. Netw., 2019
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019
2018
Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images.
J. Real Time Image Process., 2018
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.
IET Commun., 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 4th IEEE Conference on Network Softwarization and Workshops, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018
2017
Int. J. Reconfigurable Comput., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Red Lesion Detection Using Dynamic Shape Features for Diabetic Retinopathy Screening.
IEEE Trans. Medical Imaging, 2016
IET Comput. Digit. Tech., 2016
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter.
CoRR, 2016
Memory efficient and constant time 2D-recursive spatial averaging filter for embedded implementations.
Proceedings of the Real-Time Image and Video Processing 2016, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016
2015
Signal Image Video Process., 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations.
J. Signal Process. Syst., 2014
Mach. Vis. Appl., 2014
A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems.
Circuits Syst. Signal Process., 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the Medical Imaging 2014: Computer-Aided Diagnosis, 2014
Automatic detection of microaneurysms and haemorrhages in fundus images using dynamic shape features.
Proceedings of the IEEE 11th International Symposium on Biomedical Imaging, 2014
Image Deconvolution Ringing Artifact Detection and Removal via PSF Frequency Analysis.
Proceedings of the Computer Vision - ECCV 2014, 2014
A scalable hardware architecture for retinal blood vessel detection in high resolution fundus images.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Customised soft processor design: a compromise between architecture description languages and parameterisable processors.
IET Comput. Digit. Tech., 2013
A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
2012
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Mach. Vis. Appl., 2012
IET Comput. Digit. Tech., 2012
2011
Proceedings of the 2011 IEEE International Symposium on Robotic and Sensors Environments, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011
2010
J. Signal Process. Syst., 2010
Implementation methodology of embedded land vehicle positioning using an integrated GPS and multi sensor system.
Integr. Comput. Aided Eng., 2010
Two-tiered Resolution Real-Time Path Evaluation.
Proceedings of the ICEC 2010 - Proceedings of the International Conference on Evolutionary Computation, [part of the International Joint Conference on Computational Intelligence IJCCI 2010], Valencia, Spain, October 24, 2010
2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
Thermographic Body Temperature Measurement using a Mean-Shift Tracker.
Proceedings of the BIOSIGNALS 2009, 2009
2008
Measuring an Animal Body Temperature in Thermographic Video Using Particle Filter Tracking.
Proceedings of the Advances in Visual Computing, 4th International Symposium, 2008
Efficient FPGA implementation of complex multipliers using the logarithmic number system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor.
Proceedings of the 26th International Conference on Computer Design, 2008
Application Specific Instruction set processor specialized for block motion estimation.
Proceedings of the 26th International Conference on Computer Design, 2008
2007
IEEE Trans. Consumer Electron., 2007
Optimised realisations of large integer multipliers and squarers using embedded blocks.
IET Comput. Digit. Tech., 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
2003
Novel approach to the design of direct digital frequency synthesizers based on linear interpolation.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
J. VLSI Signal Process., 2002
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002