Oliver Mitea

According to our database, Oliver Mitea authored at least 5 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Fast isomorphism testing for a graph-based analog circuit synthesis framework.

Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts.

Oliver Mitea, Markus Meissner, Lars Hedrich

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Automated constraint-driven topology synthesis for analog circuits.

Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores

Proceedings of the Design, Automation and Test in Europe, 2011

2006

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.

Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner

Proceedings of the IFIP VLSI-SoC 2006, 2006

2004

A power-constrained design strategy for CMOS tuned low noise amplifiers.

Oliver Mitea, Manfred Glesner

Microelectron. Reliab., 2004