Tudor Murgan

According to our database1, Tudor Murgan authored at least 34 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
Low-Power Coding for Networks-on-Chip with Virtual Channels.
J. Low Power Electron., 2009

2008
Hardware Based Rapid Prototyping.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems.
J. Low Power Electron., 2007

Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Functional modeling techniques for a wireless LAN OFDM transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A linear model for high-level delay estimation in VDSM on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

HW/SW design and realization of a size-reconfigurable DCT accelerator.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Accurate capture of timing parameters in inductively-coupled on-chip interconnects.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Moment-Based Estimation of Switching Activity for Correlated Distributions.
Proceedings of the Integrated Circuit and System Design, 2004

On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.
Proceedings of the Integrated Circuit and System Design, 2004

Flexible Overhead Processing Architectures for G.709 Optical Transport Networks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Dynamic power optimization of the trace-back process for the Viterbi algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

The XPP Architecture and Its Co-simulation Within the Simulink Environment.
Proceedings of the Field Programmable Logic and Application, 2004

Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Proceedings of the First Conference on Computing Frontiers, 2004

Reconfigurable platforms for ubiquitous computing.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems.
Des. Autom. Embed. Syst., 2003

Transition Activity Estimation for General Correlated Data Distributions.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Moment-Based Power Estimation in Very Deep Submicron Technologies.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002


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