Sujan Pandey

According to our database, Sujan Pandey authored at least 18 papers between 2005 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Transient errors resiliency analysis technique for automotive safety critical applications.

Sujan Pandey, Bart Vermeulen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012

Soft-errors resilient logic optimization for low power.

Sujan Pandey, Klaas Brink

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2008

Process variations aware robust on-chip bus architecture synthesis for MPSoCs.

Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.

Sujan Pandey, Rolf Drechsler

Proceedings of the Design, Automation and Test in Europe, 2008

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival.

Sujan Pandey, Rolf Drechsler

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.

Sujan Pandey, Manfred Glesner

IEEE Trans. Very Large Scale Integr. Syst., 2007

Co-synthesis of custom on-chip bus and memory for MPSoC architectures.

Sujan Pandey, Christian Genz, Rolf Drechsler

Proceedings of the IFIP VLSI-SoC 2007, 2007

On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.

Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.

Sujan Pandey, Nurten Utlu, Manfred Glesner

Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.

Sujan Pandey, Tudor Murgan, Manfred Glesner

Proceedings of the IFIP VLSI-SoC 2006, 2006

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.

Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner

Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.

Sujan Pandey, Manfred Glesner

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.

Sujan Pandey, Manfred Glesner

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.

Sujan Pandey, Manfred Glesner

Proceedings of the 43rd Design Automation Conference, 2006

2005

Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.

Sujan Pandey, Manfred Glesner, Max Mühlhäuser

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip.

Thomas Hollstein, Sujan Pandey, Manfred Glesner

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

High level hardware/software communication estimation in shared memory architecture.

Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

On-Chip Communication Topology Synthesis for a Shared Memory Architecture.

Sujan Pandey, Manfred Glesner, Max Mühlhäuser

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005