Lars Hedrich

Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

2020

From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction.

[BibT_eX]

[DOI]

it Inf. Technol., 2020

Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets.

[BibT_eX]

[DOI]

Niklas Kochdumper

Malgorzata Rechmal-Lesse

Markus Olbrich

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Establishing Reachset Conformance for the Formal Analysis of Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

Numerical Simulations of Vibro-acoustic Behaviors related to Drive Train Assemblies.

[BibT_eX]

[DOI]

Yashwant Kolluru

Rolando Dölling

Proceedings of the International Symposium on Systems Engineering, 2019

Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Real-time emulation of block-based analog circuits on an FPGA.

[BibT_eX]

[DOI]

Philipp Tertel

Integr., 2018

2017

Comparing code coverage metrics for analog behavioral models.

[BibT_eX]

[DOI]

Andreas Furtig

Moritz Paschke

Proceedings of the 14th International Conference on Synthesis, 2017

Novel metrics for Analog Mixed-Signal coverage.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016

Feature based state space coverage of analog circuits.

[BibT_eX]

[DOI]

Andreas Furtig

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

FEATS: Framework for Explorative Analog Topology Synthesis.

[BibT_eX]

[DOI]

Markus Meissner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture.

[BibT_eX]

[DOI]

Integr., 2015

Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains.

[BibT_eX]

[DOI]

Tim Dackermann

Rolando Dölling

Proceedings of the IEEE International Symposium on Systems Engineering, 2015

Ageing simulation of analogue circuits and systems using adaptive transient evaluation.

[BibT_eX]

[DOI]

Felix Salfelder

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores.

[BibT_eX]

[DOI]

Julius von Rosen

Markus Meissner

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

ASDeX: a formal specification for analog circuit enabling a full automated design validation.

[BibT_eX]

[DOI]

Mingyu Ma

Swaminathan Naranayaswami

Christian Sporrer

Des. Autom. Embed. Syst., 2014

2013

Modular system-level architecture for concurrent cell balancing.

[BibT_eX]

[DOI]

Matthias Kauer

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2012

Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Analog assertion-based verification on partial state space representations using ASL.

[BibT_eX]

[DOI]

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Fast isomorphism testing for a graph-based analog circuit synthesis framework.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts.

[BibT_eX]

[DOI]

Oliver Mitea

Markus Meissner

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A machine-readable specification of analog circuits for integration into a validation flow.

[BibT_eX]

[DOI]

Mingyu Ma

Christian Sporrer

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Automated constraint-driven topology synthesis for analog circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Design and architectures for dependable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

Advanced methods for equivalence checking of analog circuits with strong nonlinearities.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2010

Improving verification coverage of analog circuit blocks by state space-guided transient simulation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Towards assertion-based verification of heterogeneous system designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Formal approaches to analog circuit verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Advanced Assertion-Based Design for Mixed-Signal Verification.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology.

[BibT_eX]

[DOI]

Xiaoying Wang

Proceedings of the Design, Automation and Test in Europe, 2008

Model Checking of Analog Systems using an Analog Specification Language.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

A symbolic approach for mixed-signal model checking.

[BibT_eX]

[DOI]

Alexander Jesser

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006

Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen.

[BibT_eX]

Ralf Klausen

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

A case study on applying bounded model checking to analog circuit verification.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Hierarchical exploration and selection of transistor-topologies for analog circuit design.

[BibT_eX]

[DOI]

Xiaoying Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis.

[BibT_eX]

[DOI]

Xiaoying Wang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Formal Verification of Analog Circuits, 2005

2004

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2002

Analog circuit sizing based on formal methods using affine arithmetic.

[BibT_eX]

[DOI]

Andreas C. Lemke

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

An Approach to Model Checking for Nonlinear Analog Systems.

[BibT_eX]

[DOI]

Walter Hartong

Proceedings of the 2002 Design, 2002

Model checking algorithms for analog verification.

[BibT_eX]

[DOI]

Walter Hartong

Proceedings of the 39th Design Automation Conference, 2002

On Discrete Modeling and Model Checking for Nonlinear Analog Systems.

[BibT_eX]

[DOI]

Walter Hartong

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2000

A current driven routing and verification methodology for analog applications.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

On the Simplification of Nonlinear DAE Systems in Analog Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the Second Workshop on Computer Algebra in Scientific Computing, 1999

1998

A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Ansätze zur formalen Verifikation analoger Schaltungen.

[BibT_eX]

[DOI]

PhD thesis, 1997

1996

Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits.

[BibT_eX]

[DOI]

Carsten Borchers

Proceedings of the 33st Conference on Design Automation, 1996

1995

A formal approach to nonlinear analog circuit verification.

[BibT_eX]

[DOI]