Oliver Weinfurtner

According to our database1, Oliver Weinfurtner authored at least 4 papers between 1998 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
Advanced controlling scheme for a DRAM voltage generator system.
IEEE J. Solid State Circuits, 2000

A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.
IEEE J. Solid State Circuits, 2000

1999
A 390-mm<sup>2</sup>, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.
IEEE J. Solid State Circuits, 1999

1998
A 220-mm<sup>2</sup>, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
IEEE J. Solid State Circuits, 1998


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