Martin Gall

According to our database1, Martin Gall authored at least 12 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Self-aligned Fiber Attach on Monolithic Silicon Photonic Chips: Moisture Effect and Hermetic Seal.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

RF long term aging behavior and reliability in 22FDX WiFi Power Amplifier designs for 5G applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2021
Strategy to Characterize Electromigration Short Length Effects in Cu/low-k Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

RF Reliability of SOI-based Power Amplifier FETs for mmWave 5G Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2018
Analysis of electromigration-induced backflow stresses in Cu(Mn) interconnects using high statistical sampling.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Analysis of 28 nm SRAM cell stability under mechanical load applied by nanoindentation.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh En§ironments.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2014
Advanced methods for mechanical and structural characterization of nanoscale materials for 3D IC integration.
Microelectron. Reliab., 2014

Empirical BEOL-TDDB evaluation based on I(t)-trace analysis.
Microelectron. Reliab., 2014

2006
Impact of stress-induced backflow on full-chip electromigration risk assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2004
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

1998
A 220-mm<sup>2</sup>, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
IEEE J. Solid State Circuits, 1998


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