Werner Weber

According to our database1, Werner Weber authored at least 19 papers between 1995 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to metal oxide semiconductors (MOS) device physics.".

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016

2015
EMC2 a Platform Project on Embedded Microcontrollers in Applications of Mobility, Industry and the Internet of Things.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2010
A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node.
IEEE J. Solid State Circuits, 2010

2009
A robust wireless sensor node for in-tire-pressure monitoring.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2005
Introduction.
Proceedings of the Ambient Intelligence, 2005

2004
Sindrion: a prototype system for low-power wireless control networks.
Proceedings of the 2004 IEEE International Conference on Mobile Ad-hoc and Sensor Systems, 2004

Embedding Low-Cost Wireless Sensors into Universal Plug and Play Environments.
Proceedings of the Wireless Sensor Networks, First European Workshop, 2004

A Self-Organizing and Fault-Tolerant Wired Peer-to-Peer Sensor Network for Textile Applications.
Proceedings of the Engineering Self-Organising Systems, 2004

2003
Electronic textiles: A platform for pervasive computing.
Proc. IEEE, 2003

Ambient Intelligence - Key Technologies in the Communication Age.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Ambient intelligence: industrial research on a visionary concept.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2001
A Mixed-Signal Design Roadmap.
IEEE Des. Test Comput., 2001

2000
Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps.
IEEE J. Solid State Circuits, 2000

A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.
IEEE J. Solid State Circuits, 2000

A robust 8F<sup>2</sup> ferroelectric RAM cell with depletion device (DeFeRAM).
IEEE J. Solid State Circuits, 2000

1999
A low-power and high-performance CMOS fingerprint sensing and encoding architecture.
IEEE J. Solid State Circuits, 1999

1997
Multiparallel systolic arrays for multidimensional FFT-architectures on 3D-VLSI.
J. Syst. Archit., 1997

1995
Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Capacitive Coupling.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Performance Improvement of the Memory Hierarchy of RISC Systems by Applications of 3-D Technology.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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