Daniel W. Storaska
According to our database1,
Daniel W. Storaska
authored at least 10 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2022
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2005
IEEE J. Solid State Circuits, 2005
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2000
IEEE J. Solid State Circuits, 2000
A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999