Oliverio J. Santana

According to our database1, Oliverio J. Santana authored at least 24 papers between 2002 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Author retrospective for software trace cache.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2010
On the Problem of Evaluating the Performance of Multiprogrammed Workloads.
IEEE Trans. Computers, 2010

Efficient runahead threads.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
DIA: A Complexity-Effective Decoding Architecture.
IEEE Trans. Computers, 2009

Code Semantic-Aware Runahead Threads.
Proceedings of the ICPP 2009, 2009

2008
Runahead Threads to improve SMT performance.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

LPA: A First Approach to the Loop Processor Architecture.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
Enlarging Instruction Streams.
IEEE Trans. Computers, 2007

Energy saving through a simple load control mechanism.
SIGARCH Computer Architecture News, 2007

FAME: FAirly MEasuring Multithreaded Architectures.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Runahead Threads: Reducing Resource Contention in SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Kilo-instruction processors, runahead and prefetching.
Proceedings of the Third Conference on Computing Frontiers, 2006

Branch predictor guided instruction decoding.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro, 2005

Multiple Stream Prediction.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004
A low-complexity fetch architecture for high-performance superscalar processors.
TACO, 2004

Toward kilo-instruction processors.
TACO, 2004

A latency-conscious SMT branch prediction architecture.
IJHPCN, 2004

Maintaining Thousands of In-flight Instructions.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Reducing Fetch Architecture Complexity Using Procedure Inlining.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
Tolerating Branch Predictor Latency on SMT.
Proceedings of the High Performance Computing, 5th International Symposium, 2003

2002
Fetching instruction streams.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A Comprehensive Analysis of Indirect Branch Prediction.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Studying New Ways for Improving Adaptive History Length Branch Predictors.
Proceedings of the High Performance Computing, 4th International Symposium, 2002


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