José F. Martínez
Orcid: 0000-0001-5451-5681Affiliations:
- Cornell University, Ithaca, NY, USA
- University of Illinois System, Urbana, IL, USA (PhD 2002)
According to our database1,
José F. Martínez
authored at least 56 papers
between 1996 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on scopus.com
-
on publons.com
-
on orcid.org
-
on dl.acm.org
On csauthors.net:
Bibliography
2023
Constraints on Research in Biological and Agricultural Science in Developing Countries: The Example of Latin America.
Publ., June, 2023
Comosum: An Extensible, Reconfigurable, and Fault-Tolerant IoT Platform for Digital Agriculture.
Proceedings of the 2023 USENIX Annual Technical Conference, 2023
PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
PIMCloud: QoS-Aware Resource Management of Latency-Critical Applications in Clouds with Processing-in-Memory.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
ReTail: Opting for Learning Simplicity to Enable QoS-Aware Power Management in the Cloud.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
2017
Workload characterization of interactive cloud services on big and small server platforms.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
ReBudget: Trading Off Efficiency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016
2015
XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
2014
Service architecting and dynamic composition in pervasive smart ecosystems for the internet of things based on sensor network technology.
J. Ambient Intell. Smart Environ., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
2013
IEEE Comput. Archit. Lett., 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2012
J. Netw. Comput. Appl., 2012
Building service-oriented Smart Infrastructures over Wireless Ad Hoc Sensor Networks: A middleware perspective.
Comput. Networks, 2012
Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture.
Proceedings of the International Conference on Supercomputing, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
2011
The DiY Smart Experiences Project - A European Endeavour Removing Barriers for User-generated Internet of Things Applications.
Proceedings of the Architecting the Internet of Things., 2011
2010
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010
2009
2008
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
2006
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Dynamic power-performance adaptation of parallel computation on chip multiprocessors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
2005
ACM Trans. Archit. Code Optim., 2005
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.
SIGARCH Comput. Archit. News, 2004
Computación y Sistemas, 2004
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
2003
IEEE Micro, 2003
IEEE Comput. Archit. Lett., 2003
2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Speculative synchronization: applying thread-level speculation to explicitly parallel applications.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002
2000
Architectural support for scalable speculative parallelization in shared-memory multiprocessors.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000
1999
Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity.
Proceedings of the 13th international conference on Supercomputing, 1999
Proceedings of the Data Warehousing and Knowledge Discovery, 1999
1996
An Interface Based on Transputers to Simulate the Dynamic Equation of Robot Manipulators Using Parallel Computing.
Proceedings of the Vector and Parallel Processing, 1996