According to our database1, Tanausú Ramírez authored at least 10 papers between 2005 and 2013.
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Capturing vulnerability variations for register files.
Proceedings of the Design, Automation and Test in Europe, 2013
New reliability mechanisms in memory design for sub-22nm technologies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Hardware/software-based diagnosis of load-store queues using expandable activity logs.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Efficient runahead threads.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
Code Semantic-Aware Runahead Threads.
Proceedings of the ICPP 2009, 2009
Runahead Threads to improve SMT performance.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Energy saving through a simple load control mechanism.
SIGARCH Computer Architecture News, 2007
Runahead Threads: Reducing Resource Contention in SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
Kilo-instruction processors, runahead and prefetching.
Proceedings of the Third Conference on Computing Frontiers, 2006
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro, 2005