Itamar Levi

According to our database1, Itamar Levi authored at least 32 papers between 2012 and 2021.

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Bibliography

2021
Hardware Private Circuits: From Trivial Composition to Full Verification.
IEEE Trans. Computers, 2021

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021

2020
Low AND Depth and Efficient Inverses: a Guide on S-boxes for Low-latency Masking.
IACR Trans. Symmetric Cryptol., 2020

Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher.
IACR Trans. Symmetric Cryptol., 2020

Ask Less, Get More: Side-Channel Signal Hiding, Revisited.
IEEE Trans. Circuits Syst., 2020

Beyond algorithmic noise or how to shuffle parallel implementations?
Int. J. Circuit Theory Appl., 2020

How Bad Are Bad Templates? Optimistic Design-Stage Side-Channel Security Evaluation and its Cost.
Cryptogr., 2020

Temporal Power Redistribution as a Countermeasure against Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019

A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs.
Integr., 2019

FPGA Implementation of pAsynch Design Paradigm.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Transient Noise Analysis of Secured Dual-Rail Based Logic Style.
Proceedings of the 2018 New Generation of CAS, 2018

Embedded randomness and data dependencies design paradigm: Advantages and challenges.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
CPA Secured Data-Dependent Delay-Assignment Methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits.
IEEE Access, 2017

Evaluation of Dual Mode Logic in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
CMOS Based Gates for Blurring Power Information.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Synthesis of Dual Mode Logic.
Integr., 2016

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Data-Dependent Delays as a Barrier Against Power Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design Flow and Characterization Methodology for Dual Mode Logic.
IEEE Access, 2015

2014
Logical Effort for CMOS-Based Dual Mode Logic Gates.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Low Energy and High Performance ${\rm DM}^{2}$ Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Low voltage dual mode logic: Model analysis and parameter extraction.
Microelectron. J., 2013

Dual Mode Logic - Design for Energy Efficiency and High Performance.
IEEE Access, 2013

2012
High speed Dual Mode Logic Carry Look Ahead Adder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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