Osamu Yamamoto

According to our database, Osamu Yamamoto authored at least 7 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Receiver diversity evaluation for a VHF band broadband mobile communication system.

Hirokazu Sawada, Masayuki Oodo, Tomoshige Kan, Fumihide Kojima, Hiroshi Harada, Hideki Kobayashi, Noriyuki Soma, Masafumi Moriyama, Osamu Yamamoto, Takaaki Yamato, Shigeki Yamamoto

Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2009

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications.

Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu

IEEE J. Solid State Circuits, 2009

2008

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.

Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto

IEEE J. Solid State Circuits, 2008

Heterogeneous multicore SoC for secure multimedia applications.

Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

IEEE J. Solid State Circuits, 2007

2006

A 40GOPS 250mW massively parallel processor based on matrix architecture.

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Implementation of Face Recognition Processing Using an Embedded Processor.

Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu

J. Robotics Mechatronics, 2005