Paul E. Landman

According to our database1, Paul E. Landman authored at least 8 papers between 1995 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2005
A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels.
IEEE J. Solid State Circuits, 2005

1997
A 1-V programmable DSP for wireless communications [CMOS].
IEEE J. Solid State Circuits, 1997

1996
Activity-sensitive architectural power analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

An Integrated CAD Environment for Low-Power Design.
IEEE Des. Test Comput., 1996

High-level power estimation.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Architectural power analysis: The dual bit type method.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Activity-sensitive architectural power analysis for the control path.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995


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