Robert Payne

According to our database, Robert Payne authored at least 18 papers between 1962 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

An efficient and resilient ultra-high speed galvanic data isolator leveraging broad-band multi resonant tank electro-magnetic coupling.

Swaminathan Sankaran, Bradley Kramer, Gregory Howard, Benjamin Sutton, Randall Walberg, Vijaylaxmi Khanolkar, Robert Payne, Mark Morgan

Proceedings of the Symposium on VLSI Circuits, 2015

2014

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC.

Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright

IEEE J. Solid State Circuits, 2014

2013

A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS.

Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee

IEEE Trans. Very Large Scale Integr. Syst., 2013

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs.

Xiaochen Yang, Robert Payne, Jin Liu

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee.

Robert Payne, Tatsuya Saito

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC.

Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Good, bad, ugly - 20 years of broadband evolution: What's next?

Jerry Lin, Franz Dielacher, Jing-Hong Conan Zhan, Robert Payne

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR.

Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor

IEEE J. Solid State Circuits, 2010

Energy-efficient high-speed interfaces.

Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR.

Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Will ADCs overtake binary frontends in backplane signaling?

Ali Sheikholeslami, Robert Payne

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS.

Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Future of High-Speed Transceivers (Forum).

Robert Payne

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Multi-GB/s Transceivers.

Robert Payne, Muneo Fukaishi

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels.

Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee

IEEE J. Solid State Circuits, 2005

1999

Panel: What is the Proper System on Chip Design Methodology.

Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani

Proceedings of the 36th Conference on Design Automation, 1999

1997

Self-timed field programmmable gate array architectures.

Robert Payne

PhD thesis, 1997

1962

Online digital computer measurement of a neurological control system.

Lawrence Stark, Robert Payne, Yutaka Okabe

Commun. ACM, 1962