Letícia Maria Veiras Bolzani
Orcid: 0000-0002-6043-1713Affiliations:
- RWTH Aachen University, Germany
According to our database1,
Letícia Maria Veiras Bolzani
authored at least 93 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.
J. Electron. Test., 2021
J. Electron. Test., 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
2020
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects.
J. Electron. Test., 2020
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.
Proceedings of the IEEE Latin-American Test Symposium, 2020
2019
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects.
J. Electron. Test., 2019
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture.
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
2018
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
2016
Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
Microelectron. Reliab., 2016
Selected Peer Reviewed Articles from the 17th "IEEE Latin-American Test Symposium, " Foz do Iguaçu, Brazil, April 6-8, 2016.
J. Low Power Electron., 2016
J. Electron. Test., 2016
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time.
J. Electron. Test., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 13th IEEE International Conference on Networking, Sensing, and Control, 2016
2015
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013.
J. Low Power Electron., 2014
J. Electron. Test., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
2013
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices.
Proceedings of the 14th Latin American Test Workshop, 2013
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Reliability analysis of an on-chip watchdog for embedded systems exposed to radiation and EMI.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.
J. Low Power Electron., 2011
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity.
Proceedings of the 12th Latin American Test Workshop, 2011
An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 16th European Test Symposium, 2011
2010
IEEE Trans. Dependable Secur. Comput., 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
A software-based methodology for the generation of peripheral test sets based on high-level descriptions.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007
2006
IEEE Trans. Computers, 2006
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
2005
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
2003
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003