Peter Flake

According to our database, Peter Flake authored at least 9 papers between 1983 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Verilog HDL and its ancestors and descendants.

Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann

Proc. ACM Program. Lang., 2020

2013

Systemc infrastructure and extensions.

Peter Flake, Frank Oppenheimer

Proceedings of the 2013 Forum on specification and Design Languages, 2013

Why SystemVeriog?

Peter Flake

Proceedings of the 2013 Forum on specification and Design Languages, 2013

2006

System-level exploration tools for MPSoC designs.

Peter Flake, Simon J. Davidmann, Frank Schirrmeister

Proceedings of the 43rd Design Automation Conference, 2006

2004

SystemC and SystemVerilog: Where do They Fit? Where are They Going?

Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji

Proceedings of the 2004 Design, 2004

2001

Panel: Your Core - My Problem? Integration and Verification of IP.

Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake

Proceedings of the 38th Design Automation Conference, 2001

2000

One language or more?: how can we design an SoC at a system level?

Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura

Proceedings of ASP-DAC 2000, 2000

Superlog, a unified design language for system-on-chip.

Peter Flake, Simon J. Davidmann

Proceedings of ASP-DAC 2000, 2000

1983

An algebra for logic strength simulation.

Peter Flake, Philip Moorby, Gerry Musgrave

Proceedings of the 20th Design Automation Conference, 1983