Peter Sagazio

Orcid: 0000-0001-7335-5337

According to our database1, Peter Sagazio authored at least 8 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, December, 2023

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW.
IEEE J. Solid State Circuits, 2023

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, 2022

A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Architecture and Circuit Choices for 5G Millimeter-Wave Beamforming Transceivers.
IEEE Commun. Mag., 2018


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