Somnath Kundu
Orcid: 0000-0002-5891-7968
According to our database1,
Somnath Kundu
authored at least 37 papers
between 2012 and 2024.
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Bibliography
2024
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, December, 2023
Theor. Comput. Sci., 2023
IEEE J. Solid State Circuits, 2023
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2023
Proceedings of the 27th International Conference on Methods and Models in Automation and Robotics, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the Algorithmics of Wireless Networks - 19th International Symposium, 2023
2022
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021
Proceedings of the Combinatorial Algorithms - 32nd International Workshop, 2021
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Evacuating from ℓ<sub>p</sub> Unit Disks in the Wireless Model - (Extended Abstract).
Proceedings of the Algorithms for Sensor Systems, 2021
2020
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer.
IEEE J. Solid State Circuits, 2019
Proceedings of the 23rd International Conference on Principles of Distributed Systems, 2019
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the Game Theory for Networks, 2019
2018
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer.
IEEE J. Solid State Circuits, 2018
A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.0094mm<sup>2</sup>/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 0.0054-mm<sup>2</sup> Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012