Amy Whitcombe

Orcid: 0000-0002-7188-7628

According to our database1, Amy Whitcombe authored at least 11 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, December, 2023

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW.
IEEE J. Solid State Circuits, 2023

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, 2022

A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016
Design of Energy- and Cost-Efficient Massive MIMO Arrays.
Proc. IEEE, 2016

On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS.
Proceedings of the 46th European Solid-State Device Research Conference, 2016


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