Philip Jacob

Affiliations:
  • IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
  • Rensselaer Polytechnic Institute, USA (PhD 2010)


According to our database1, Philip Jacob authored at least 11 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU.
IEEE Access, 2015

2011
Carry Chains for Ultra High-Speed SiGe HBT Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications.
IET Circuits Devices Syst., 2011

2010
Serial code accelerators for heterogeneous multi-core processor with 3D stacked memory.
PhD thesis, 2010

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology".
IEEE J. Solid State Circuits, 2010

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2010

2009
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Proc. IEEE, 2009

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
Predicting the Performance of a 3D Processor-Memory Chip Stack.
IEEE Des. Test Comput., 2005


  Loading...