Aamir Zia

According to our database1, Aamir Zia authored at least 9 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Design of BiCMOS SRAMs for high-speed SiGe applications.
IET Circuits Devices Syst., 2014

2012
A three-dimensional DRAM using floating body cell in FDSOI devices.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
3D NOC for many-core processors.
Microelectron. J., 2011

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications.
IET Circuits Devices Syst., 2011

2010
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Proc. IEEE, 2009

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
Predicting the Performance of a 3D Processor-Memory Chip Stack.
IEEE Des. Test Comput., 2005


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