Philip Ostrovskyy

Orcid: 0009-0009-0393-2528

According to our database1, Philip Ostrovskyy authored at least 8 papers between 2012 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2025
A 50 Gb/s Rad-Hard Quad TIA IC for Onboard Satellite Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Area-Efficient Digital Design Using RRAM-CMOS Standard Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023
Advanced Quality Assurance Platform for Robust Process Design Kits.
Proceedings of the VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence, 2023

Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

LUT-based RRAM Model for Neural Accelerator Circuit Simulation.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2014
High-speed continuous-time band pass ΔΣ modulator for class-S systems.
Microelectron. J., 2014

2012
A fully digital polar modulator for switch mode RF power amplifier.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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