Jianan Wen

Orcid: 0009-0003-7733-8907

According to our database1, Jianan Wen authored at least 15 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2026

RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026

End-to-End Design Flow for Resistive Neural Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

2025
FsimNNs: An Open-Source Graph Neural Network Platform for SEU Simulation-based Fault Injection.
CoRR, November, 2025

A Compact One-Transistor-Multiple-RRAM Characterization Platform.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025

RISC-V CPU Design Using RRAM-CMOS Standard Cells.
IEEE Trans. Very Large Scale Integr. Syst., September, 2025

ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators.
Proceedings of the 31st IEEE International Symposium on On-Line Testing and Robust System Design, 2025

2024
HyRPF: Hybrid RRAM Prototyping on FPGA.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2024

Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

LUT-based RRAM Model for Neural Accelerator Circuit Simulation.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022
Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020


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