Dietmar Fey

Orcid: 0000-0002-6077-4732

Affiliations:
  • University of Erlangen-Nuremberg, Germany


According to our database1, Dietmar Fey authored at least 191 papers between 1992 and 2023.

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Bibliography

2023
Optimizing multi-level ReRAM memory for low latency and low energy consumption.
it Inf. Technol., May, 2023

Memristive computing in Germany.
it Inf. Technol., May, 2023

Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures.
IEEE Comput. Archit. Lett., 2023

Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing.
Proceedings of the 13th International Conference on Simulation and Modeling Methodologies, 2023

Hyper Dimensional Computing with Ferroelectric Tunneling Junctions.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2022
Investigating SAMV Regarding its Suitability For FPGAs.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

2021
Adaptation Strategies for Personalized Gait Neuroprosthetics.
Frontiers Neurorobotics, 2021

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems.
IEEE Access, 2021

Fault Tolerance in Heterogeneous Automotive Real-time Systems.
Proceedings of the Echtzeit 2021, 2021

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design.
Proceedings of the 24th IEEE International Symposium on Real-Time Distributed Computing, 2021

Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

A Case for Function-as-a-Service with Disaggregated FPGAs.
Proceedings of the 14th IEEE International Conference on Cloud Computing, 2021

2020
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors.
Supercomput. Front. Innov., 2020

The allscale framework architecture.
Parallel Comput., 2020

Memristoren für zukünftige Rechnersysteme.
Inform. Spektrum, 2020

Impact of Performance Estimation on Fast Processor Simulators.
Proceedings of the Simulation Tools and Techniques - 12th EAI International Conference, 2020

Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation.
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Direct state transfer in MLC based memristive ReRAM devices for ternary computing.
Proceedings of the European Conference on Circuit Theory and Design, 2020

TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands.
J. Signal Process. Syst., 2019

Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms.
J. Signal Process. Syst., 2019

Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications.
J. Signal Process. Syst., 2019

Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing.
Proceedings of the IEEE 4th International Workshops on Foundations and Applications of Self* Systems, 2019

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

A Hardware Inference Accelerator for Temporal Convolutional Networks.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Generic Functional Simulation of Heterogeneous Systems.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Guest Editorial Memristive-Device-Based Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A programmable ternary CPU using hybrid CMOS/memristor circuits.
Int. J. Parallel Emergent Distributed Syst., 2018

IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures.
J. Real Time Image Process., 2018

An extended analysis of memory hierarchies for efficient implementations of image processing applications.
J. Real Time Image Process., 2018

Special issue on heterogeneous real-time image processing.
J. Real Time Image Process., 2018

Case study on memristor-based multilevel memories.
Int. J. Circuit Theory Appl., 2018

On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors.
Proceedings of the High Performance Computing - 33rd International Conference, 2018

A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Multi-level memristive voltage divider: programming scheme trade-offs.
Proceedings of the International Symposium on Memory Systems, 2018

The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Autonomous Driving in the Curriculum of Computer Architecture.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems.
Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018

Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

The AllScale Runtime Application Model.
Proceedings of the IEEE International Conference on Cluster Computing, 2018

A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Fast heterogeneous computing architectures for smart antennas.
J. Syst. Archit., 2017

Introduction to the special issue on architecture of computing systems.
J. Syst. Archit., 2017

Comprehensive curriculum for reconfigurable heterogeneous computer architecture education.
IET Circuits Devices Syst., 2017

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach.
CoRR, 2017

Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms.
Concurr. Comput. Pract. Exp., 2017

Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors.
Concurr. Comput. Pract. Exp., 2017

Memristive devices for computing: Beyond CMOS and beyond von Neumann.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors.
Proceedings of the High Performance Computing - 32nd International Conference, 2017

System on chip generation for multi-sensor and sensor fusion applications.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Prototyping memristors in digital system with an FPGA-based testing environment.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops.
Proceedings of the International Symposium on Memory Systems, 2017

Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure.
Proceedings of the 4th Workshop on CrossCloud Infrastructures & Platforms, CrossCloud@EuroSys 2017, Belgrade, Serbia, April 23, 2017

The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors.
CoRR, 2016

Closing the Performance Gap with Modern C++.
Proceedings of the High Performance Computing, 2016

Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU.
Proceedings of the 9th EAI International Conference on Simulation Tools and Techniques, 2016

Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware.
Proceedings of the 6th International Conference on Simulation and Modeling Methodologies, 2016

Hardware-software Co-simulation of Self-organizing Smart Home Networks - Who am I and Where Are the Others?.
Proceedings of the 6th International Conference on Simulation and Modeling Methodologies, 2016

Improving instruction accurate simulation for parallel automotive applications.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors.
Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, 2016

The AllScale Runtime Interface - Theoretical Foundation and Concept.
Proceedings of the 9th Workshop on Many-Task Computing on Clouds, 2016

Hybrid code description for developing fast and resource efficient image processing architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Dataflow optimization for programmable embedded image preprocessing accelerators.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits.
Proceedings of the Second International Symposium on Memory Systems, 2016

C++ Classes and Templates for OpenCL Kernels with PATOS.
Proceedings of the 4th International Workshop on OpenCL, 2016

An Application-Specific Instruction Set Processor for Power Quality Monitoring.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Evaluating Performance and Energy-Efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures.
Proceedings of the International Conference on Computational Science 2016, 2016

Teaching heterogeneous computer architectures using smart camera systems.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

Investigation of strategies for an increasing population size in multi-objective CMA-ES.
Proceedings of the IEEE Congress on Evolutionary Computation, 2016

Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Synthesis and optimization of image processing accelerators using domain knowledge.
J. Syst. Archit., 2015

OpenCL 2.0 for FPGAs using OCLAcc.
CoRR, 2015

Automatic Optimization of Hardware Accelerators for Image Processing.
CoRR, 2015

Performance analysis of the Kahan-enhanced scalar product on current multicore processors.
CoRR, 2015

Execution-Cache-Memory Performance Model: Introduction and Validation.
CoRR, 2015

A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures.
CoRR, 2015

Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015).
CoRR, 2015

SmartEco: An Integrated Solution from Load Balancing between the Grid and Consumers to Local Energy Efficiency.
Proceedings of the 8th IEEE/ACM International Conference on Utility and Cloud Computing, 2015

FREACSIM: a framework for creating and simulating real-time capable network on chip systems and applications.
Proceedings of the 8th International Conference on Simulation Tools and Techniques, 2015

Hardware-software co-simulation for medical x-ray control units.
Proceedings of the 8th International Conference on Simulation Tools and Techniques, 2015

Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures.
Proceedings of the Simulation and Modeling Methodologies, Technologies and Applications, 2015

Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation.
Proceedings of the SIMULTECH 2015 - Proceedings of the 5th International Conference on Simulation and Modeling Methodologies, Technologies and Applications, Colmar, Alsace, France, 21, 2015

Higher-level parallelization for local and distributed asynchronous task-based programming.
Proceedings of the First International Workshop on Extreme Scale Programming Models and Middleware, 2015

Framework for parameter analysis of FPGA-based image processing architectures.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

FAUPU - A design framework for the development of programmable image processing architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Architecture and simulation of a hybrid memristive multiplier network using redundant number representation.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Real-time correlation for locating systems utilizing heterogeneous computing architectures.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
Services for numerical simulations and optimisations in grids.
Int. J. Parallel Emergent Distributed Syst., 2014

Fast image processing for optical metrology utilizing heterogeneous computer architectures.
Comput. Electr. Eng., 2014

Fast and generic hardware architecture for stereo block matching applications on embedded systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A Portable Petascale Framework for Efficient Particle Methods with Custom Interactions.
Proceedings of the 21st European MPI Users' Group Meeting, 2014

HPX: A Task Based Programming Model in a Global Address Space.
Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models, 2014

A Generic Approach for Analysis of White-Light Interferometry Data via User-Defined Algorithms.
Proceedings of the Computational Science and Its Applications - ICCSA 2014 - 14th International Conference, Guimarães, Portugal, June 30, 2014

Designing and manufacturing of real embedded multi-core CPUs: A holistic teaching approach in computer architecture.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Performance Investigation and Tuning in the Interoperable Cloud4E Platform.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

On the Way to Big Data Applications in Industrial Computed Tomography.
Proceedings of the 2014 IEEE International Congress on Big Data, Anchorage, AK, USA, June 27, 2014

2013
Performance investigations of genetic algorithms on graphics cards.
Swarm Evol. Comput., 2013

Using HPX and LibGeoDecomp for scaling HPC applications on heterogeneous supercomputers.
Proceedings of the Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems, 2013

An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Smart sensor architectures for embedded biosignal analysis.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Optical multiplexing techniques for photonic Clos networks in High Performance Computing Architectures.
J. Supercomput., 2012

Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware.
Concurr. Comput. Pract. Exp., 2012

A Predictive Performance Model for Stencil Codes on Multicore CPUs.
Proceedings of the High Performance Computing for Computational Science, 2012

Zero-Overhead Interfaces for High-Performance Computing Libraries and Kernels.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Heterogeneous computer architectures: An image processing pipeline for optical metrology.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

The empirically refined competence structure model for embedded micro- and nanosystems.
Proceedings of the Annual Conference on Innovation and Technology in Computer Science Education, 2012

A Generic VHDL Template for 2D Stencil Code Applications on FPGAs.
Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2012

Optimization of a Short-Range Proximity Effect Correction Algorithm in E-Beam Lithography Using GPGPUs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Evolutionary Design of Active Free Space Optical Networks Based on Digital Mirror Devices.
Proceedings of the Applications of Evolutionary Computation, 2012

Competence model for embedded micro-and nanosystems.
Proceedings of the IEEE Global Engineering Education Conference, 2012

A Speed-Up Study for a Parallelized White Light Interferometry Preprocessing Algorithm on a Virtual Embedded Multiprocessor System.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Performance comparison of designated preprocessing white light interferometry algorithms on emerging multi- and many-core architectures.
Proceedings of the International Conference on Computational Science, 2011

High Performance Stencil Code Algorithms for GPGPUs.
Proceedings of the International Conference on Computational Science, 2011

Parallel simulation of dendritic growth on unstructured grids.
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

A normative competence structure model for embedded micro- and nanosystems development.
Proceedings of the 16th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2011

Analytical Model for the Optimization of Self-Organizing Image Processing Systems Utilizing Cellular Automata.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Evolutionary optimization of layouts for high density free space optical network links.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

Competence research: teaching embedded micro/nano systems.
Proceedings of the 6th Workshop on Embedded Systems Education, 2011

Generic Emergent Computing in Chip Architectures.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

Emergent Computing with Marching Pixels for Real-Time Smart Camera Applications.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

2010
Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices (Unkonventionelles Rechnen - reversible Addierer für künftiges Nanocomputing).
it Inf. Technol., 2010

Seamless high speed simulation of VHDL components in the context of comprehensive computing systems using the virtual machine faumachine.
Proceedings of the 2010 Winter Simulation Conference, 2010

An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Simulation and Optimized Design of High Density Optical Crossconnect Systems for Massively Parallel Computing Architectures.
Proceedings of the Optical Supercomputing - Third International Workshop, 2010

Realizing Real-Time Centroid Detection of Multiple Objects with Marching Pixels Algorithms.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

Framework for Distributed Evolutionary Algorithms in Computational Grids.
Proceedings of the Advances in Computation and Intelligence - 5th International Symposium, 2010

Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Marching Pixels - Rechnen mit Hardware-Agenten im 2D Pixelraum.
Proceedings of the 40. Jahrestagung der Gesellschaft für Informatik, Service Science - Neue Perspektiven für die Informatik, INFORMATIK 2010, Leipzig, Germany, September 27, 2010

Revising the Trade-off between the Number of Agents and Agent Intelligence.
Proceedings of the Applications of Evolutionary Computation, 2010

Dynamically Programmable Image Processor for Compact Vision Systems.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Model-Driven Design and Organic Computing -- Two Different but Possibly Accordable Concepts for the Design of Embedded Systems.
Proceedings of the 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2009

Herausforderungen der Technischen Informatik beim Unkonventionellen Rechnen.
Proceedings of the 39. Jahrestagung der Gesellschaft für Informatik, Im Focus das Leben, INFORMATIK 2009, Lübeck, Germany, September 28, 2009

Evaluating the evolvability of emergent agents with different numbers of states.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

On the Effectiveness of Evolution Compared to Time-Consuming Full Search of Optimal 6-State Automata.
Proceedings of the Genetic Programming, 12th European Conference, 2009

Distributed vision with smart pixels.
Proceedings of the 25th ACM Symposium on Computational Geometry, 2009

2008
LibGeoDecomp: A Grid-Enabled Library for Geometric Decomposition Codes.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

A Profitability Heuristic that Reduces the Parameter Dependence of Dynamic Load Balancing.
Proceedings of the Informatiktage 2008, 2008

Challenges of MPI over IPv6.
Proceedings of the Fourth International Conference on Networking and Services, 2008

Pollarder: An Architecture Concept for Self-adapting Parallel Applications in Computational Science.
Proceedings of the Computational Science, 2008

Emergent algorithms for centroid and orientation detection in high-performance embedded cameras.
Proceedings of the 5th Conference on Computing Frontiers, 2008

Solving the problem of enforced restriction to few states while evolving cellular automata.
Proceedings of the Automata 2008: Theory and Applications of Cellular Automata, 2008

2007
Realising emergent image preprocessing tasks in cellular-automaton-alike massively parallel hardware.
Int. J. Parallel Emergent Distributed Syst., 2007

A Virtual Test Environment for MPI Development: Quick Answers to Many Small Questions.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 14th European PVM/MPI User's Group Meeting, Paris, France, September 30, 2007

Comparison of Evolving Uniform, Non-uniform Cellular Automaton, and Genetic Programming for Centroid Detection with Hardware Agents.
Proceedings of the Parallel Computing Technologies, 2007

An Organic Computing architecture for visual microprocessors based on Marching Pixels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

SOGOS - A Distributed Meta Level Architecture for the Self-Organizing Grid of Services.
Proceedings of the 7th International Conference on Mobile Data Management (MDM 2006), 2006

Parallelization of Simulations for Various Magnetic System Models on Small-Sized Cluster Computers with MPI.
Proceedings of the Computational Science and Its Applications, 2006

2005
Calculation of Single-File Diffusion Using Grid-Enabled Parallel Generic Cellular Automata Simulation.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2005

Marching-pixels: a new organic computing paradigm for smart sensor processor arrays.
Proceedings of the Second Conference on Computing Frontiers, 2005

Marching Pixels: A new Organic Computing Prinicple for Smart CMOS Camera Chips.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
A Framework for Optimising Parameter Studies on a Cluster Computer by the Example of Micro-system Design.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2004

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras.
Proceedings of the ARCS 2004, 2004

2003
OptoRAP - eine rekonfigurierbare optoelektronische Parallelprozessor-Architektur für die Bildvorverarbeitung (OptoRAP - a Reconfigurable Optoelectronic Parallel Processor Architecture for Image Pre-Processing).
it Inf. Technol., 2003

Optotechnologie in der IT.
it Inf. Technol., 2003

2002
Optik in der Rechentechnik - photonisches VLSI und optische Netzwerke.
Teubner-Texte zur Informatik 35, Teubner, ISBN: 978-3-519-00338-0, 2002

2001
A digital multi-layer-perceptron hardware architecture based on three dimensional massively parallel optoelectronic circuits.
Informatica (Slovenia), 2001

2000
Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.
J. Supercomput., 2000

Optical interconnects for neural and reconfigurable VLSI architectures.
Proc. IEEE, 2000

1999
Architekturen und Entwurfssysteme für ein optoelektronisches 3-D VLSI.
Informationstechnik Tech. Inform., 1999

3D Optoelectronic Fix Point Unit and Its Advantages Processing 3D Data.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Massively Parallel Volume Rendering by Exploiting a 3d Optoelectronic Arithmetic Logical Unit.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999

1996
Principles for Optoelectronic 3D Architectures and Correponding Algorithms to Calculate Standard Functions.
Proceedings of the Parcella 1996, 1996

Transformation of a 2-D VLSI Systolic Adder Circuit in 3-D Circuits Using Optical Interconnections.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1994
Parallele digitale optische Recheneinheiten - Modellierung, Simulation und Bewertung.
Teubner, ISBN: 978-3-519-02293-0, 1994

1993
Modellierung, Simulation und Bewertung paralleler digitaler optischer Systeme.
PhD thesis, 1993

1992
Architekturkonzepte für massiv-parallele, opto-elektronische Rechnersysteme.
Proceedings of the Architektur von Rechensystemen, 1992


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