Daniel Reiser

Orcid: 0000-0003-0212-259X

According to our database1, Daniel Reiser authored at least 6 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
Thermal switching of TiO<sub>2</sub>-based RRAM for parameter extraction and neuromorphic engineering.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Fast HBM Access with FPGAs: Analysis, Architectures, and Applications.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

2020
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2013
A Framework for Interoperability Testing in Pan-European Public Service Provision.
Proceedings of the Electronic Government - 12th IFIP WG 8.5 International Conference, 2013


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