Philip P. Shirvani

According to our database1, Philip P. Shirvani authored at least 7 papers between 1999 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Estimating Silent Data Corruption Rates Using a Two-Level Model.
CoRR, 2020

2018
Low Overhead Tag Error Mitigation for GPU Architectures.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

2002
Control-flow checking by software signatures.
IEEE Trans. Reliab., 2002

Error detection by duplicated instructions in super-scalar processors.
IEEE Trans. Reliab., 2002

2000
Software-implemented EDAC protection against SEUs.
IEEE Trans. Reliab., 2000

DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
PADded Cache: A New Fault-Tolerance Technique for Cache Memories.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999


  Loading...