Vincenzo Della Marca
According to our database1,
Vincenzo Della Marca
authored at least 12 papers
between 2012 and 2023.
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Bibliography
2023
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2021
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
2020
AC stress reliability study of a new high voltage transistor for logic memory circuits.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
True random number generation exploiting SET voltage variability in resistive RAM memory arrays.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
2018
Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction.
Microelectron. Reliab., 2018
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2014
Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories.
Microelectron. Reliab., 2014
2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012