Pascal Masson
According to our database1,
Pascal Masson
authored at least 14 papers
between 2004 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2018
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2015
Dynamic current reduction of CMOS digital circuits through design and process optimization.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Investigation of the effects of constant voltage stress on thin SiO<sub>2</sub> layers using dynamic measurement protocols.
Microelectron. Reliab., 2012
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEICE Trans. Electron., 2005
2004
Proceedings of the 2004 Design, 2004