U. Fat Chio

According to our database, U. Fat Chio authored at least 35 papers between 2004 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery.

Wen-Liang Zeng, Edoardo Bonizzoni, Chi-Wa U, Chi-Seng Lam, Sai-Weng Sin, U. Fat Chio, Franco Maloberti, Rui Paulo Martins

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging.

Ji-Xuan Li, Sai-Weng Sin, U. Fat Chio, Ya-Jie Wu, Chi-Seng Lam, Rui Paulo Martins

IEEE Trans. Circuits Syst., 2020

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.

Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang

J. Circuits Syst. Comput., 2020

2019

A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.

Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery.

U-Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins

IEEE J. Solid State Circuits, 2019

2017

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.

Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang

IEEE Trans. Very Large Scale Integr. Syst., 2017

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators.

U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology.

Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai-Weng Sin, Rui Paulo Martins

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2014

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization.

Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

IEEE J. Solid State Circuits, 2013

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.

Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.

He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti

IEEE J. Solid State Circuits, 2012

A 0.024 mm² 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS.

Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins

Proceedings of the 38th European Solid-State Circuit conference, 2012

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique.

Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins

Proceedings of the 38th European Solid-State Circuit conference, 2012

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC.

Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 0.024mm² 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.

He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration.

U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators.

Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.

Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs.

Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

VLSI Design, 2010

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS.

He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC.

U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.

Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti

IEEE J. Solid State Circuits, 2010

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.

Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.

Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang

Proceedings of the 17th IEEE International Conference on Electronics, 2010

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.

Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2008

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch.

Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants.

Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen

Microelectron. J., 2008

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.

He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs.

Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.

He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.

U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR.

Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A multiparameter implantable microstimulator SOC.

Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh

IEEE Trans. Very Large Scale Integr. Syst., 2005

2004

A C-less ASK demodulator for implantable neural interfacing chips.

Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004