Prashant D. Joshi

According to our database, Prashant D. Joshi authored at least 11 papers between 2008 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2022

Aging Effects On Clock Gated Memory Phase Paths.

Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2020

Validation Challenges in Recent Trends of Power Management in Microprocessors.

Nagabhushan Reddy, Sankaran Menon, Prashant D. Joshi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

High Performance Memory Repair.

Feroze Merchant, Anandraj Devarajan, Anik Basu, David Ashen, Brandon Yelton, Prashant D. Joshi

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2017

Tight Bounds in Message Delays Despite Faults in a Class of Line Digraph Networks.

Prashant D. Joshi, D. Frank Hsu, Arunabha Sen, Said Hamdioui, Koen Bertels

Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Region based containers - A new paradigm for the analysis of fault tolerant networks.

Prashant D. Joshi, Arunabha Sen, D. Frank Hsu, Said Hamdioui, Koen Bertels

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2014

Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures.

Prashant D. Joshi, Said Hamdioui

Proceedings of the IEEE 15th International Conference on High Performance Switching and Routing, 2014

Shortest path reduction in a class of uniform fault tolerant networks.

Prashant D. Joshi, Said Hamdioui

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Security methods in fault tolerant modified line graph based networks.

Prashant D. Joshi, Said Hamdioui

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks.

Prashant D. Joshi, Arunabha Sen, Said Hamdioui, Koen Bertels

Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2013

Guest Editorial.

Prashant D. Joshi, Massimo Violante

J. Electron. Test., 2013

2008

Error Detect Logic Resulting in Faster Address Generate and Decode for Caches.

Prashant D. Joshi

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008