Prassanna Sithambaram

According to our database, Prassanna Sithambaram authored at least 12 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.

Prassanna Sithambaram, Alberto Macii, Enrico Macii

J. Embed. Comput., 2009

2008

Thermal-Aware Design Techniques for Nanometer CMOS Circuits.

Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino

J. Low Power Electron., 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Integr., 2008

2007

New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.

Prassanna Sithambaram, Alberto Macii, Enrico Macii

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Dynamic thermal clock skew compensation using tunable delay buffers.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal resilient bounded-skew clock tree optimization methodology.

Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.

Prassanna Sithambaram, Alberto Macii, Enrico Macii

Proceedings of the Integrated Circuit and System Design, 2005

Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.

Prassanna Sithambaram, Alberto Macii, Enrico Macii

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005