Ashoka Visweswara Sathanur
According to our database1,
Ashoka Visweswara Sathanur
authored at least 22 papers
between 2006 and 2012.
Collaborative distances:
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Bibliography
2012
Microelectron. J., 2012
2011
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
2010
Automatic synthesis of near-threshold circuits with fine-grained performance tunability.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.
J. Low Power Electron., 2009
Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
J. Low Power Electron., 2008
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integr., 2008
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006