Quan Deng

Orcid: 0000-0002-1454-8486

Affiliations:
  • National University of Defense Technology, Changsha, China


According to our database1, Quan Deng authored at least 18 papers between 2015 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Vector Value Prediction with Element-wise Stride Compression.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025
PFP: Parallel Floating-Point Vector Multiplication Acceleration in MAGIC ReRAM.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
SSC: An SRAM-Based Silence Computing Design for On-chip Memory.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2024

A Novel Efficient Maximum Searching Algorithm in ReRAM Array.
Proceedings of the Euro-Par 2024: Parallel Processing Workshops, 2024

ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

2023
Fast Approximate LUT-based Vector Multiplication in DRAM.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

2020
A Memristor-Based Spiking Neural Network With High Scalability and Learning Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
DWMAcc: Accelerating Shift-based CNNs with Domain Wall Memories.
ACM Trans. Embed. Comput. Syst., 2019

PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

RFAcc: a 3D ReRAM associative array based random forest accelerator.
Proceedings of the ACM International Conference on Supercomputing, 2019

LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
DrAcc: a DRAM based accelerator for accurate CNN inference.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Mitigate erroneous operations of 2T-2MTJ STT-MRAM based on dynamic voltage threshold.
IEICE Electron. Express, 2016

A Novel Separated Pre-discharging Sense Amplifier for STT-MRAM.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

2015
SEU hardened layout design for SRAM cells based on SEU reversal.
IEICE Electron. Express, 2015

Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015


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