Lei Jiang
Orcid: 0000-0003-4795-0284Affiliations:
- Indiana University Bloomington, USA
According to our database1,
Lei Jiang
authored at least 78 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on jianglei.org
On csauthors.net:
Bibliography
2023
IEEE Trans. Computers, February, 2023
CoRR, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
QDoor: Exploiting Approximate Synthesis for Backdoor Attacks in Quantum Neural Networks.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted Data.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2022
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
QMLP: An Error-Tolerant Nonlinear Quantum MLP Architecture using Parameterized Two-Qubit Gates.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
MATCHA: a fast and energy-efficient accelerator for fully homomorphic encryption over the torus.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
HEMET: A Homomorphic-Encryption-Friendly Privacy-Preserving Mobile Neural Network Architecture.
Proceedings of the 38th International Conference on Machine Learning, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the 2021 Conference on Empirical Methods in Natural Language Processing, 2021
2020
AutoPrivacy: Automated Layer-wise Parameter Selection for Secure Neural Network Inference.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Proceedings of the 8th International Conference on Learning Representations, 2020
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Helix: Algorithm/Architecture Co-design for Accelerating Nanopore Genome Base-calling.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM.
IEEE Trans. Computers, 2019
SHE: A Fast and Accurate Privacy-Preserving Deep Neural Network Via Leveled TFHE and Logarithmic Data Representation.
CoRR, 2019
CoRR, 2019
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
IEEE Comput. Archit. Lett., 2018
BRAWL: A Spintronics-Based Portable Basecalling-in-Memory Architecture for Nanopore Genome Sequencing.
IEEE Comput. Archit. Lett., 2018
Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018
3DICT: a reliable and QoS capable mobile process-in-memory architecture for lookup-based CNNs in 3D XPoint ReRAMs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embed. Comput. Syst., 2017
Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture.
CoRR, 2017
Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication.
IEEE Comput. Archit. Lett., 2017
High-Performance Massive Subgraph Counting Using Pipelined Adaptive-Group Communication.
Proceedings of the Big Data and HPC: Ecosystem and Convergence, TopHPC 2017, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017
2016
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.
ACM Trans. Design Autom. Electr. Syst., 2015
Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015
SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015
2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.
ACM Trans. Archit. Code Optim., 2013
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013
2012
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011
2010
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2010
2008
Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture.
Microprocess. Microsystems, 2008