Minxuan Zhang

According to our database1, Minxuan Zhang authored at least 72 papers between 2003 and 2019.

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Bibliography

2019
LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
DrAcc: a DRAM based accelerator for accurate CNN inference.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system.
IEICE Electronic Express, 2016

Sub-threshold Performance Driven Choice in Tunneling CNFETs.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

A Novel L1 Cache Based on Volatile STT-RAM.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

A New DVFS Algorithm Design for Multi-core Processor Chip.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Hardware design of ML algorithm in MIMO-OFDM system.
Proceedings of the 3rd International Conference on Systems and Informatics, 2016

A Novel Hybrid Last Level Cache Based on Multi-retention STT-RAM Cells.
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015
Exploring partitioning methods for multicast in 3D bufferless Network on Chip.
IEICE Electronic Express, 2015

SEU hardened layout design for SRAM cells based on SEU reversal.
IEICE Electronic Express, 2015

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system.
IEICE Electronic Express, 2015

Towards high-performance packet processing on commodity multi-cores: current issues and future directions.
SCIENCE CHINA Information Sciences, 2015

Partitioning Methods for Multicast in Bufferless 3D Network on Chip.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Impact of Heavy Ion Species and Energy on SEE Characteristics of Three-Dimensional Integrated Circuit.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Improved access pattern for ROB soft error rate mitigation based on 3D integration technology.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method.
IEEE Trans. VLSI Syst., 2014

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells.
IEICE Electronic Express, 2014

Assimilating Cleaning Operations with Flash-Level Parallelism for NAND Flash-Based Devices.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.
IEEE Trans. VLSI Syst., 2013

Architecture and Implementation of a Reduced EPIC Processor.
IEICE Transactions, 2013

Wormhole Bubble in Torus Networks.
Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013

An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Adaptive Capacity Sharing through Probabilistic Controlled Placement.
JCP, 2012

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.
IEICE Transactions, 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.
IEICE Transactions, 2012

Accurate and Simplified Prediction of L2 Cache Vulnerability for Cost-Efficient Soft Error Protection.
IEICE Transactions, 2012

A single-cycle output buffered router with layered switching for Networks-on-Chips.
Computers & Electrical Engineering, 2012

PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture.
Proceedings of the Seventh IEEE International Conference on Networking, 2012

Adaptive Bubble Scheme with Minimal Buffers in Torus Networks.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

An Efficient Hardware Random Number Generator Based on the MT Method.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs.
Computing and Informatics, 2011

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Characterizing Time-Varying Behavior and Predictability of Cache AVF.
Proceedings of the 2011 Third International Conference on Intelligent Networking and Collaborative Systems (INCoS), Fukuoka, Japan, November 30, 2011

Accelerating the Extraction of Representative Behaviors of Programs with Dynamic Binary Translation.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Timing-Driven Routing of High Fanout Nets.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Evaluation of deflection routing on various NoC topologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs.
IEICE Transactions, 2010

Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy.
SCIENCE CHINA Information Sciences, 2010

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A high performance router with dynamic buffer allocation for on-chip interconnect networks.
Proceedings of the 28th International Conference on Computer Design, 2010

Towards Online Application Cache Behaviors Identification in CMPs.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

Low Power Design for a Multi-core Multi-thread Microprocessor.
Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications, 2010

Phase Characterization and Classification for Micro-architecture Soft Error.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

2009
A Global Replacement Based on Actual Set Association.
Proceedings of the International Conference on Embedded Software and Systems, 2009

2008
Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007
A Parallel Infrastructure on Dynamic EPIC SMT and Its Speculation Optimization.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Register File Management and Compiler Optimization on EDSMT.
Proceedings of the Frontiers of High Performance Computing and Networking ISPA 2007 Workshops, 2007

Hardware-Based Multicast with Global Load Balance on k-ary n-trees.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

A Parallel Infrastructure on Dynamic EPIC SMT.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2007

A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor.
Proceedings of the 2007 International Conference on Computer Design, 2007

Look-Ahead Adaptive Routing on k -Ary n -Trees.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

2006
Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy.
Proceedings of the Seventh International Conference on Parallel and Distributed Computing, 2006

An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Enhancing DCache Warn Fetch Policy for SMT Processors.
Proceedings of the Parallel and Distributed Processing and Applications, 2005

Detecting Memory Access Errors with Flow-Sensitive Conditional Range Analysis.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors.
Proceedings of the Advanced Parallel Processing Technologies, 6th International Workshop, 2005

2004
Dual-Stack Return Address Predictor.
Proceedings of the Embedded Software and Systems, First International Conference, 2004

2003
Reconfigurable Cipher Processing Framework and Implementation.
Proceedings of the Advanced Parallel Programming Technologies, 5th International Workshop, 2003


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