Weixia Xu
Orcid: 0009-0007-6327-7372Affiliations:
- National University of Defense Technology (NUDT), College of Computer Science and Technology, Changsha, China (PhD 1999)
According to our database1,
Weixia Xu authored at least 52 papers
between 1997 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2025
IEEE Trans. Intell. Transp. Syst., August, 2025
NeuCore: A Novel Neuromorphic Processor Architecture With On-Chip Event-Driven Learning.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2025
Hardware/Software Co-design for spike communication optimization: Leveraging neuron-level communication patterns.
J. Syst. Archit., 2025
J. Parallel Distributed Comput., 2025
Integr., 2025
2024
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign.
ACM Trans. Archit. Code Optim., September, 2024
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
2023
J. Comput. Sci. Technol., December, 2023
Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA.
IEEE Trans. Parallel Distributed Syst., November, 2023
ACM Trans. Archit. Code Optim., March, 2023
2022
LSMCore: A 69k-Synapse/mm<sup>2</sup> Single-Core Digital Neuromorphic Processor for Liquid State Machine.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
J. Syst. Archit., 2022
Revisiting network congestion avoidance through adaptive packet-chaining reservation.
Comput. Networks, 2022
2021
Quingo: A Programming Framework for Heterogeneous Quantum-Classical Computing with NISQ Features.
ACM Trans. Quantum Comput., December, 2021
Integr., 2021
Neurocomputing, 2021
2020
A Memristor-Based Spiking Neural Network With High Scalability and Learning Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
ACM Trans. Archit. Code Optim., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array.
J. Comput. Sci. Technol., 2020
CoRR, 2020
CoRR, 2020
CoRR, 2020
A Noise Filter for Dynamic Vision Sensors based on Global Space and Time Information.
CoRR, 2020
Exploration of Input Patterns for Enhancing the Performance of Liquid State Machines.
CoRR, 2020
CompressedCache: Enabling Storage Compression on Neuromorphic Processor for Liquid State Machine.
Proceedings of the Network and Parallel Computing, 2020
SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Application-specific network-on-chip design space exploration framework for neuromorphic processor.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
2019
ACM Trans. Archit. Code Optim., 2019
PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array.
Proceedings of the Network and Parallel Computing, 2019
2018
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018
2017
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017
Proceedings of the 2017 IEEE International Conference on Signal Processing, 2017
2016
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016
Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016
2012
Distributed Coverage in Wireless Ad Hoc and Sensor Networks by Topological Graph Approaches.
IEEE Trans. Computers, 2012
2011
J. Comput. Sci. Technol., 2011
Proceedings of the Fifth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2011
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2010
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
1997
Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997