Weixia Xu

Orcid: 0009-0007-6327-7372

Affiliations:
  • National University of Defense Technology (NUDT), College of Computer Science and Technology, Changsha, China (PhD 1999)


According to our database1, Weixia Xu authored at least 52 papers between 1997 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Bayesian Procedures for Modeling Truck Route Choices.
IEEE Trans. Intell. Transp. Syst., August, 2025

NeuCore: A Novel Neuromorphic Processor Architecture With On-Chip Event-Driven Learning.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2025

Hardware/Software Co-design for spike communication optimization: Leveraging neuron-level communication patterns.
J. Syst. Archit., 2025

A lightweight RDMA connection protocol based on post-hoc confirmation.
J. Parallel Distributed Comput., 2025

Optimizing value prediction for ILP processors: A design space exploration approach.
Integr., 2025

EgDiff: An Enhanced Global Load Value Predictor.
IEEE Comput. Archit. Lett., 2025

2024
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign.
ACM Trans. Archit. Code Optim., September, 2024

Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Cost-Effective Value Predictor for ILP processors through Design Space Exploration.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
M-LSM: An Improved Multi-Liquid State Machine for Event-Based Vision Recognition.
J. Comput. Sci. Technol., December, 2023

Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA.
IEEE Trans. Parallel Distributed Syst., November, 2023

SSD-SGD: Communication Sparsification for Distributed Deep Learning Training.
ACM Trans. Archit. Code Optim., March, 2023

2022
LSMCore: A 69k-Synapse/mm<sup>2</sup> Single-Core Digital Neuromorphic Processor for Liquid State Machine.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware-aware liquid state machine generation for 2D/3D Network-on-Chip platforms.
J. Syst. Archit., 2022

Large-scale full-programmable quantum walk and its applications.
CoRR, 2022

Revisiting network congestion avoidance through adaptive packet-chaining reservation.
Comput. Networks, 2022

Stride Equality Prediction for Value Speculation.
IEEE Comput. Archit. Lett., 2022

2021
Quingo: A Programming Framework for Heterogeneous Quantum-Classical Computing with NISQ Features.
ACM Trans. Quantum Comput., December, 2021

A multi-objective LSM/NoC architecture co-design framework.
J. Syst. Archit., 2021

HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor.
Integr., 2021

A neural architecture search based framework for liquid state machine design.
Neurocomputing, 2021

Evolutionary Recurrent Neural Architecture Search.
IEEE Embed. Syst. Lett., 2021

2020
A Memristor-Based Spiking Neural Network With High Scalability and Learning Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

OD-SGD: One-Step Delay Stochastic Gradient Descent for Distributed Training.
ACM Trans. Archit. Code Optim., 2020

ASIE: An Asynchronous SNN Inference Engine for AER Events Processing.
ACM J. Emerg. Technol. Comput. Syst., 2020

SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array.
J. Comput. Sci. Technol., 2020

ssd-sgd: communication sparsification for distributed deep learning training.
CoRR, 2020

SeqXFilter: A Memory-efficient Denoising Filter for Dynamic Vision Sensors.
CoRR, 2020

OD-SGD: One-step Delay Stochastic Gradient Descent for Distributed Training.
CoRR, 2020

A Noise Filter for Dynamic Vision Sensors based on Global Space and Time Information.
CoRR, 2020

Exploration of Input Patterns for Enhancing the Performance of Liquid State Machines.
CoRR, 2020

CompressedCache: Enabling Storage Compression on Neuromorphic Processor for Liquid State Machine.
Proceedings of the Network and Parallel Computing, 2020

SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Application-specific network-on-chip design space exploration framework for neuromorphic processor.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Liquid State Machine Applications Mapping for NoC-Based Neuromorphic Platforms.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2019
SketchDLC: A Sketch on Distributed Deep Learning Communication via Trace Capturing.
ACM Trans. Archit. Code Optim., 2019

PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array.
Proceedings of the Network and Parallel Computing, 2019

2018
A Power Efficient Hardware Implementation of the IF Neuron Model.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018

2017
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Heterogeneous acceleration for CNN training with many integrated core.
Proceedings of the 2017 IEEE International Conference on Signal Processing, 2017

2016
Monaural Speech Separation on Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

2012
Distributed Coverage in Wireless Ad Hoc and Sensor Networks by Topological Graph Approaches.
IEEE Trans. Computers, 2012

2011
Optimizing Linpack Benchmark on GPU-Accelerated Petascale Supercomputer.
J. Comput. Sci. Technol., 2011

A Formalization of an Emulation Based Co-designed Virtual Machine.
Proceedings of the Fifth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2011

A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
TH-1: China's first petaflop supercomputer.
Frontiers Comput. Sci. China, 2010

A Novel Chaining Approach for Direct Control Transfer Instructions.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

1997
A Dual-Processors Multithreaded Architecture and Its Driven Execution Model.
Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997


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