Quang-Kien Trinh

Orcid: 0000-0002-0499-2938

According to our database1, Quang-Kien Trinh authored at least 29 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
NUTS-BSNN: A non-uniform time-step binarized spiking neural network with energy-efficient in-memory computing macro.
Neurocomputing, December, 2023

LNA linearization solution for direct conversion receiver using under-sampling technique in reference receiver.
Phys. Commun., August, 2023

A low-power charge-based integrate-and-fire circuit for binarized-spiking neural network.
Int. J. Circuit Theory Appl., July, 2023

Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA.
EAI Endorsed Trans. Ind. Networks Intell. Syst., 2023

Sleep Apnea Patient Monitoring Using Continuous-wave Radar.
Proceedings of the IEEE Statistical Signal Processing Workshop, 2023

A Novel Efficient Hardware Implementation of Symbol Timing and Carrier Phase Synchronizer for QPSK Receivers.
Proceedings of the 12th International Conference on Control, 2023

Uncovering the Resilience of Binarized Spiking Neural Networks under Adversarial Attacks.
Proceedings of the 12th International Conference on Control, 2023

2022
A LUT-based scheme for LNA linearization in direct RF sampling receivers.
Phys. Commun., 2022

A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA.
Integr., 2022

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A Novel In-memory Matching Circuit Based on Non-volatile Resistive Memory.
Proceedings of the International Conference on IC Design and Technology, 2022

FBW-SNN: A Fully Binarized Weights-Spiking Neural Networks for Edge-AI Applications.
Proceedings of the International Conference on IC Design and Technology, 2022

An Effective Design Approach to Implementation of MIMO-SDM-PNC Relay Stations on FPGA.
Proceedings of the 11th International Conference on Control, 2022

2021
STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM.
IEEE Access, 2021

An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Stabilizing On-chip Secure Key Generation Using RO-PUF.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021

2020
Feasibility and Design Trade-Offs of Neural Network Accelerators Implemented on Reconfigurable Hardware.
Proceedings of the Industrial Networks and Intelligent Systems, 2020

2019
Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUF.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Novel Distortion Compensation Scheme for Multichannel Direct RF Digitization Receiver.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

2018
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Novel Time-Based Sensing Scheme for STT-MRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Boosted sensing for enhanced read stability in STT-MRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015


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