Rachel Selina Rajarathnam

Orcid: 0000-0001-6383-9709

According to our database1, Rachel Selina Rajarathnam authored at least 8 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection.
CoRR, 2024

Automated Physical Design Watermarking Leveraging Graph Neural Networks.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Better Together: Combining Analytical and Annealing Methods for FPGA Placement.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023
DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints.
CoRR, 2023

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs.
Proceedings of the 2023 International Symposium on Physical Design, 2023

2022
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2020
ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020


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