Vaughn Betz

According to our database1, Vaughn Betz authored at least 112 papers between 1995 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs.
IEEE Trans. Computers, 2022

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices.
IEEE Access, 2022

2021
Optimizing Interstitial Photodynamic Therapy Planning With Reinforcement Learning-Based Diffuser Placement.
IEEE Trans. Biomed. Eng., 2021

StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
Optimizing FPGA Logic Block Architectures for Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies.
IEEE Trans. Very Large Scale Integr. Syst., 2020

VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling.
ACM Trans. Reconfigurable Technol. Syst., 2020

FPGA Logic Block Architectures for Efficient Deep Learning Inference.
ACM Trans. Reconfigurable Technol. Syst., 2020

Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching.
ACM Trans. Reconfigurable Technol. Syst., 2020

SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs.
IEEE Micro, 2020

From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware Generation.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

StateReveal: Enabling Checkpointing of FPGA Designs with Buried State.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

AIR: A Fast but Lazy Timing-Driven FPGA Router.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
The Costs of Confidentiality in Virtualized FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2019

FRoC 2.0: Automatic BRAM and Logic Testing to Enable Dynamic Voltage Scaling for FPGA Applications.
ACM Trans. Reconfigurable Technol. Syst., 2019

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Safe Task Interruption for FPGAs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors.
ACM Trans. Reconfigurable Technol. Syst., 2018

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Wotan: Evaluating FPGA Architecture Routability without Benchmarks.
ACM Trans. Reconfigurable Technol. Syst., 2018

You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference.
ACM Trans. Reconfigurable Technol. Syst., 2018

Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability.
IEEE Trans. Ind. Electron., 2018

Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays.
IEEE Access, 2018

HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Improving Confidentiality in Virtualized FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Latency Insensitive Design Styles for FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Design and Applications for Embedded Networks-on-Chip on FPGAs.
IEEE Trans. Computers, 2017

Automatic circuit design and modelling for heterogeneous FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2017

Quantifying and mitigating the costs of FPGA virtualization.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Find the real speed limit: FPGA CAD for chip-specific application delay measurement.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Quantifying error: Extending static timing analysis with probabilistic transitions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System.
ACM Trans. Reconfigurable Technol. Syst., 2016

High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Measure twice and cut once: Robust dynamic voltage scaling for FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

LYNX: CAD for FPGA-based networks-on-chip.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD.
ACM Trans. Reconfigurable Technol. Syst., 2015

Robust Optimization of Multiple Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

HETRIS: Adaptive floorplanning for heterogeneous FPGAs.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Design and simulation tools for Embedded NOCs on FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Take the Highway: Design for Embedded NoCs on FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design.
IEEE Trans. Very Large Scale Integr. Syst., 2014

VTR 7.0: Next Generation Architecture and CAD System for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2014

Networks-on-Chip for FPGAs: Hard, Soft or Mixed?
ACM Trans. Reconfigurable Technol. Syst., 2014

The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays.
IEEE Micro, 2014

Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Cad and routing architecture for interposer-based multi-FPGA systems.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Quantifying the cost and benefit of latency insensitive communication on FPGAs.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

On Hard Adders and Carry Chains in FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Speeding Up FPGA Placement: Parallel Algorithms and Methods.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Efficient and programmable ethernet switching with a NoC-enhanced FPGA.
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014

2013
Efficient methods for out-of-order load/store execution for high-performance soft processors.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

COFFE: Fully-automated transistor sizing for FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

From Quartus to VPR: Converting HDL to BLIF with the Titan flow.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Titan: Enabling large and complex benchmarks in academic CAD.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Should FPGAS abandon the pass-gate?
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

The power of communication: Energy-efficient NOCS for FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Are FPGAs suffering from the innovator's dilemna?
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
Portable and scalable FPGA-based acceleration of a direct linear system solver.
ACM Trans. Reconfigurable Technol. Syst., 2012

Design tradeoffs for hard and soft FPGA-based Networks-on-Chip.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Efficient and Deterministic Parallel Placement for FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2011

FPGAs, Programming Models, and Kit Cars.
IEEE Des. Test Comput., 2011

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Recent FPGA Advances and Challenges.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
FPGA challenges and opportunities at 40nm and beyond.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

FPGA Synthesis and Physical Design.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

High-quality, deterministic parallel placement for FPGAs on commodity hardware.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Power-aware RAM mapping for FPGA embedded memory blocks.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

2004
Simultaneous short-path and long-path timing optimization for FPGAs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
The Stratix<sup>TM</sup> routing and logic architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2000
Speed and area tradeoffs in cluster-based FPGA architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Timing-driven placement for FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Automatic generation of FPGA routing architectures from high-level descriptions.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Architecture and CAD for Deep-Submicron FPGAS
The Springer International Series in Engineering and Computer Science 497, Kluwer, ISBN: 978-1-4615-5145-4, 1999

1998
Effect of the prefabricated routing track distribution on FPGA area-efficiency.
IEEE Trans. Very Large Scale Integr. Syst., 1998

How Much Logic Should Go in an FPGA Logic Block?
IEEE Des. Test Comput., 1998

A Fast Routability-Driven Router for FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
VPR: A new packing, placement and routing tool for FPGA research.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1996
Directional bias and non-uniformity in FPGA global routing architectures.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Using Architectural "Families" to Increase FPGA Speed and Density.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995


  Loading...