Radhakrishnan Sithanandam

According to our database, Radhakrishnan Sithanandam authored at least 4 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Technology Scaling of ESD Devices in State of the Art FinFET Technologies.

Sukjin Kim, Radhakrishnan Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyukhoon Kwon, Namho Kim, Chanhee Jeon

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2015

Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics.

N. K. Kranthi, Radhakrishnan Sithanandam, Rama Komaragiri

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor.

Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2010

A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications.

Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010