Rafael Reif

Affiliations:
  • Massachusetts Institute of Technology, Cambridge, USA


According to our database1, Rafael Reif authored at least 11 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1993, "For pioneering work in the low-temperature epitaxial growth of semiconductor thin films.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2005
Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Calibration of Rent's rule models for three-dimensional integrated circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Technology, performance, and computer-aided design of three-dimensional integrated circuits.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Timing, energy, and thermal performance of three-dimensional integrated circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Wiring requirement and three-dimensional integration technology for field programmable gate arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Design tools for 3-D integrated circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Fabrication Technologies for Three-Dimensional Integrated Circuits (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001
Interconnect limits on gigascale integration (GSI) in the 21st century.
Proc. IEEE, 2001

Wiring requirement and three-dimensional integration of field-programmable gate arrays.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000
System-level performance evaluation of three-dimensional integrated circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000


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