Jose Renau

According to our database, Jose Renau authored at least 61 papers between 2000 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Multi-threaded Fast Hardware Compiler for HDLs.

Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau

Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

2021

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation.

Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

LiveHD: A Productive Live Hardware Development Flow.

Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau

IEEE Micro, 2020

Load Driven Branch Predictor (LDBP).

Akash Sridhar, Nursultan Kabylkas, Jose Renau

CoRR, 2020

LiveSim: A Fast Hot Reload Simulator for HDLs.

Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

EMI Architectural Model and Core Hopping.

Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SMatch: Structural Matching for Fast Resynthesis in FPGAs.

Rafael Trapani Possignolo, Jose Renau

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

GPU NTC Process Variation Compensation With Voltage Stacking.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau

IEEE Trans. Very Large Scale Integr. Syst., 2018

Automated Pipeline Transformations with Fluid Pipelines.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau

Proceedings of the Advanced Logic Synthesis, 2018

2017

Architectural opportunities for novel dynamic EMI shifting (DEMIS).

Daphne I. Gorman, Matthew R. Guthaus, Jose Renau

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Liam: an actor based programming model for HDLs.

Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau

Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Level shifter design for voltage stacking.

Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Timing speculative SRAM.

Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Managing Mismatches in Voltage Stacking with CoreUnfolding.

Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau

ACM Trans. Archit. Code Optim., 2016

Analysis of PARSEC workload scalability.

Gabriel Southern, Jose Renau

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

SRAM voltage stacking.

Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Overhead of deoptimization checks in the V8 javascript engine.

Gabriel Southern, Jose Renau

Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

LiveSim: Going live with microarchitecture simulation.

Sina Hassani, Gabriel Southern, Jose Renau

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

LiveSynth: Towards an interactive synthesis flow.

Rafael Trapani Possignolo, Jose Renau

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015

Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication.

Madan Mohan Das, Gabriel Southern, Jose Renau

ACM Trans. Archit. Code Optim., 2015

Message from the program chair.

Jose Renau

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014

Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices.

Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation.

Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, Jose Renau

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An energy efficient GPGPU memory hierarchy with tiny incoherent caches.

Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

ESESC: A fast multicore simulator using Time-Based Sampling.

Ehsan K. Ardestani, Jose Renau

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

ESESC: A fast performance, power, and temperature multicore simulator.

Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012

Thermal-aware sampling in architectural simulation.

Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011

ReRack: power simulation for data centers with renewable energy generation.

Michael Brown, Jose Renau

SIGMETRICS Perform. Evaluation Rev., 2011

Hot Chips 22.

Jose Renau, Will Eatherton

IEEE Micro, 2011

A design time simulator for computer architects.

Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Releasing efficient beta cores to market early.

Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

Characterizing processor thermal behavior.

Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

SOI, interconnect, package, and mainboard thermal characterization.

Joseph Nayfach-Battilana, Jose Renau

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Measuring and modeling variabilityusing low-cost FPGAs.

Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Understanding bug fix patterns in verilog.

Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau

Proceedings of the 2008 International Working Conference on Mining Software Repositories, 2008

Processor Verification with hwBugHunt.

Sangeetha Sudhakrishnan, Liying Su, Jose Renau

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Measuring power and temperature from real processors.

Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

System and Procesor Design Effort Estimation.

Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Estimating design time for system circuits.

Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau

Proceedings of the IFIP VLSI-SoC 2007, 2007

Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.

Francisco J. Mesa-Martinez, Jose Renau

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Power model validation through thermal measurements.

Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Measuring performance, power, and temperature from real processors.

Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau

Proceedings of the Workshop on Experimental Computer Science, 2007

2006

CAVA: Using checkpoint-assisted value prediction to hide L2 misses.

Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau

ACM Trans. Archit. Code Optim., 2006

Energy-Efficient Thread-Level Speculation.

Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas

IEEE Micro, 2006

POSH: a TLS compiler that exploits program structure.

Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006

SEED: scalable, efficient enforcement of dependences.

Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

uComplexity: Estimating Processor Design Effort.

Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.

Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas

Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Thread-Level Speculation on a CMP can be energy efficient.

Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas

Proceedings of the 19th Annual International Conference on Supercomputing, 2005

2004

Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency

Jose Renau

PhD thesis, 2004

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.

Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas

IEEE Comput. Archit. Lett., 2004

2003

Programming the FlexRAM parallel intelligent memory system.

Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2003

Positional Adaptation of Processors: Application to Energy Reduction.

Michael C. Huang, Jose Renau, Josep Torrellas

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002

Cherry: checkpointed early resource recycling in out-of-order microprocessors.

José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-efficient hybrid wakeup logic.

Michael C. Huang, Jose Renau, Josep Torrellas

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management.

Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas

J. Instr. Level Parallelism, 2001

L1 data cache decomposition for energy efficiency.

Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

A framework for dynamic energy efficiency and temperature management.

Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.

Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas

Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000