Rajeev Jayaraman

According to our database, Rajeev Jayaraman authored at least 8 papers between 1988 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs.

Priya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2002

Guest editorial.

Majid Sarrafzadeh, Rajeev Jayaraman

ACM Trans. Design Autom. Electr. Syst., 2002

2001

Physical design for FPGAs.

Rajeev Jayaraman

Proceedings of the 2001 International Symposium on Physical Design, 2001

Panel: (When) Will FPGAs Kill ASICs?

Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen

Proceedings of the 38th Design Automation Conference, 2001

2000

A Placement Algorithm for FPGA Designs with Multiple I/O Standards.

Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman

Proceedings of the Field-Programmable Logic and Applications, 2000

1998

A Novel Predictable Segmented FPGA Routing Architecture.

Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1991

A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.

Rajeev Jayaraman, Rob A. Rutenbar

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1988

Error tolerance in parallel simulated annealing techniques.

Rajeev Jayaraman, Frederica Darema

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988